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Signal Integrity and High-Speed Interconnects January-May 2006 An Overview on Signal Integrity Dr. José Ernesto Rayas Sánchez 1 Outline Review of market and technology trends A Signal Integrity (SI) definition An introduction to SI terminology Dr. J.E. Rayas Sánchez 2 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Technology Trends The minimum dimension of transistors has been continuously decreasing: 25 µm in 1960 to 0.13µm in 2005 The number of transistors per chip has continue to double every 1.5 year (Moore’s law) CPU operating frequency has continuously increase Denser and faster buses have appeared Faster memories are required Cost of interconnects remain a small fraction (<5%) of the system cost Dr. J.E. Rayas Sánchez 3 Decreasing Dimension of Transistors Dr. J.E. Rayas Sánchez 4 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Decreasing Dimension of Transistors (cont) Dr. J.E. Rayas Sánchez 5 Decreasing Dimension of Transistors (cont) State-of-the-art silicon transistors can operate above 1 THz Dr. J.E. Rayas Sánchez 6 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Moore’s Law Dr. J.E. Rayas Sánchez 7 CPU Operating Frequency Processor Frequency Frequency 10000 4004 8008 8080 8085 1000 8086 Frequency [MHz] 8088 80186 100 80286 80386 486DX 486DX2 10 486DX4 Pentium® Pentium® Pro Pentium® II 1 Celeron® Pentium® III Pentium® 4 0.1 1970 1975 1980 1985 1990 Year 1995 2000 2005 2010 (H. Heck, 2005) 8 Dr. J.E. Rayas Sánchez Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Denser and Faster Buses 486DX2 Processor (~1992) Pentium® 4 Processor (2003) ▪ 3 major buses ▪ 33 MHz max frequency ▪ 4 byte bus width ▪ 4 major buses ▪ 66-800 MHz max frequency ▪ 4-16 byte bus width CPU 100 MHz 32 bit 33 MHz FPM/EDO DRAM 32 bit 12 MHz PCI Chipset L2 Cache 32 bit 33 MHz PCI Slots (H. Heck, 2005) 9 Dr. J.E. Rayas Sánchez Denser and Faster Buses (cont) System Bus Frequency System Bus Frequency 1000 4004 8008 8080 8085 8086 100 Frequency [MHz] 8088 80186 80286 80386 10 486DX 486DX2 486DX4 Pentium® Pentium® Pro 1 Pentium® II Celeron® Pentium® III Pentium® 4 0.1 1970 1975 1980 1985 1990 Year 1995 2000 2005 2010 (H. Heck, 2005)10 Dr. J.E. Rayas Sánchez Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Faster and Denser Memories Peak Bandwidth [MB/s] 10000 1000 100 10 2001 1999 1997 1995 1993 1991 1989 1987 1985 1983 1981 1 Year (H. Heck, 2005)11 Dr. J.E. Rayas Sánchez Cost of Interconnects Interconnect makes up < 5% of the system cost – Most technical problems can be solved with $ – High volume PC market can’t afford extra cost Designing Multi-GHz interconnects to fit in sub $1000 PCs is a huge challenge Approximate Cost Breakdown of a PC Motherboard & Connectors (< 5% of total) O/S Fax/Modem CDROM Sound + Case Speakers Memory Hard Disk CPU Monitor + Video Card Power Supply Dr. J.E. Rayas Sánchez Motherboard Components Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx (H. Heck, 2005)12 Signal Integrity and High-Speed Interconnects January-May 2006 Cost of Interconnects (cont) FR4 has been the standard choice for PCBs in the last four decades Other dielectrics have better performance: polyethylene (PE), polytetrafluoroethylene (PTFE) PTFE-based laminates can cost up to US$100 per squared foot FR4 is US$2/sq ft (D. Reed, 2003)13 Dr. J.E. Rayas Sánchez High-Speed Digital Design Physical design becomes crucial: connectors, backplanes, packages, PCB structures, material properties, etc. Analog techniques (analog electronics, RF and microwave engineering) are used to solve most signal integrity problems © Copyright 2003 Agilent Technologies, Inc. Dr. J.E. Rayas Sánchez 14 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 High-Speed Digital Design (cont) Eye Diagrams (for a 25-inch channel) 1 Gbps, 200 psec/div 2.5 Gbps, 80 psec/div 5 Gbps, 40 psec/div 7.5 Gbps, 27 psec/div © Copyright 2003 Agilent Technologies, Inc. Dr. J.E. Rayas Sánchez 15 What is Signal Integrity (SI)? It is an engineering practice that aims at ensuring reliable high-speed data transmission and reception, without polluting the electromagnetic spectrum and without damaging any device SI effectively combines concepts and techniques from the following disciplines: – – – – – – microwave and RF engineering electromagnetics physical design analog electronics communications, and digital design Dr. J.E. Rayas Sánchez 16 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 SI Problems Appear at Different Levels (M. Nakhla, 2004)17 Dr. J.E. Rayas Sánchez SI Problems Appear at Different Levels (cont) Dr. J.E. Rayas Sánchez (A. Weisshaar, 2004)18 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Effective Signal Integrity Practices Tracking down the cause of signal integrity problems after the hardware has been created can be extremely complicated (R. Mellitz, 2003)19 Dr. J.E. Rayas Sánchez Signal Integrity Issues Dr. J.E. Rayas Sánchez 20 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Tools and Concepts for Signal Integrity Issues Dr. J.E. Rayas Sánchez 21 CAD Tools for SI CAD tools allow addressing many signal integrity issues during simulation Appropriate simulation strategies improve the understanding of highly complex signal integrity phenomena If the simulation is accurate enough, many signal integrity problems can be solved before they actually exist Dr. J.E. Rayas Sánchez 22 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx Signal Integrity and High-Speed Interconnects January-May 2006 Conclusions System performance and functionality increase over time In the PC market, sales decrease sharply when the price exceeds the volume desktop price barrier Interconnect components account for < 5% of system cost Interconnects impose severe limitations in system performance Interconnect engineers must satisfy increased performance demands without increasing the cost of the solution SI problems are challenging, but many tools and concepts can be used to alleviate them Dr. J.E. Rayas Sánchez 23 Dr. J. E. Rayas Sánchez http://iteso.mx/~erayas erayas@iteso.mx
